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TSMC's 3-D chip packaging technology will be mass produced in 2021: for 5-nm process, Apple or the first time

via:Expreview超能网     time:2019/4/22 14:08:30     readed:349

As the world's largest wafer manufacturer, TSMC's technology in semiconductor manufacturing has nothing to say, but many people do not know that TSMC has increased the research and development of semiconductor packaging technology in recent years. Over the past few years, the exclusive manufacturing of Apple A series processors is also related to their packaging technology progress. Recently, at the talk conference of TSMC, co-CEO Wei Zhejia revealed that TSMC has completed the first 3D IC packaging in the world, and is expected to produce in 2021. It is known that the technology is mainly oriented to the future 5nm process, and the most likely to launch the 3D packaging technology is Apple, its biggest customer.

Samsung once shared Apple's orders with TSMC in the A9 processor, but since the A10 processor, TSMC has been the exclusive manufacturer, and TSMC has won Apple's favor not only because of semiconductor manufacturing technology, but also because TSMC can integrate advanced packaging technology.

In the case of the gradual failure of Moore's Law of Semiconductor Manufacturing, it is not easy to rely solely on manufacturing process to improve chip integration and reduce cost, so advanced packaging technology has developed rapidly in recent years. Earlier, TSMC introduced Fan Out Wafer Level Packaging (InFO WLP) and CoWoS packaging technology, which made the chip have better electrical characteristics, can achieve higher memory bandwidth and low power operation capability, and can make mobile devices have better performance and lower power consumption.

However, InFO WLP and CoWoS are essentially 2.5D packaging. The industry has been pursuing true 3D packaging. Last year, TSMC announced the launch of Wafer-on-Wafer (WoW) packaging technology, which realizes real 3D packaging through TSV silicon piercing technology. This packaging technology is mainly used for future 7Nm and 5nm replacement processes.

Although TSMC did not explicitly mention whether their first 3D IC process was Wafer-on-Wafer (WoW) packaging technology at last week's presentation meeting, guess it is this new technology. After all, 3D packaging is a popular new technology in 2019. Intel's Foreros packaging is also a kind of 3D chip packaging.

According to TSMC, their 3D IC packaging technology has been developed, but will not be mass produced until 2021, when their main technology is 5nm EUV level. As for which customer has become the first to eat crabs, Apple is expected to be the first company to use TSMC 3-D packaging. In the past, Apple was the first to use TSMC 2.5D packaging. They have this demand and this capital.

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