OpenASIP: Tools for design and programming of customized co-processors

OpenASIP: Tools for design and programming of customized co-processors cpc / openasip Public Notifications You must be signed in to change notification settings Fork 54 Star 195 Branches Tags Open more actions menu Latest commit History 4,626 Commits 4,626 Commits Folders and files Name Name Last commit message Last commit date .github/ workflows .github/ workflows openasip openasip testsuite testsuite .gitignore .gitignore CONTRIBUTING.md CONTRIBUTING.md LICENSE.txt LICENSE.txt README.md README.md Repository files navigation OpenASIP - Open Application-Specific Instruction-set Processor toolset OpenASIP is an open application-specific instruction-set processor (ASIP) toolset for design and programming of customized co-processors (typically programmable accelerators). The toolset provides a complete retargetable co-design flow from high-level language programs down to FPGA/ASIC synthesizable processor RTL (VHDL and Verilog generation supported) and instruction-parallel program binaries.

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• cpc / openasip Public Notifications You must be signed in to change notification settings Fork 54 Star 195 Branches Tags Open more actions menu Latest commit History 4,626 Commits 4,626 Commits Folders and files Name Name Last commit message Last commit date .github/ workflows .github/ workflows openasip openasip testsuite testsuite .gitignore .gitignore CONTRIBUTING.md CONTRIBUTING.md LICENSE.txt LICENSE.txt README.md README.md Repository files navigation OpenASIP - Open Application-Specific Instruction-set Processor toolset OpenASIP is an open application-specific instruction-set processor (ASIP) toolset for design and programming of customized co-processors (typically programmable accelerators).
• The toolset provides a complete retargetable co-design flow from high-level language programs down to FPGA/ASIC synthesizable processor RTL (VHDL and Verilog generation supported) and instruction-parallel program binaries.
• Processor customization points include the register files, function units, supported operations, and the datapath interconnection network.
• The internal processor template of OpenASIP is based on the energy efficient and modular Transport Triggered Architecture (TTA), which is still its default target programming model for static multi-issue designs.
• OpenASIP, however, also has initial support for other programming models such as standard operation-based VLIW (demonstrated in Blocks CGRA) and in 2.0 it got the first features to support customizing RISC-V ISA based processors.
• OpenASIP has been developed by several researchers (and research assistants) of Tampere University (Finland) and various other international contributors since the early 2003.